TSMC unveils upcoming processes

TSMC has unveiled  its latest technologies for advanced logic, specialty, and 3D ICs including the nanosheet-based N2 process and  FINFLEX technology for the N3 and N3E processes making their debut..  

“We are living in a rapidly changing, supercharged, digital world where demand for computational power and energy efficiency is growing faster than ever before, creating unprecedented opportunities and challenges for the semiconductor industry,” says CEO  C.C. Wei, “the  innovations demonstrate TSMC’s technology leadership and our commitment to support our customers through this exciting period of transformation and growth.”

 FINFLEX for N3 and N3E – TSMC’s N3 process, set to enter volume production later in 2022, will feature the revolutionary  FINFLEX architectural innovation offering unparalleled flexibility for designers. It  offers choices of different standard cells with a 3-2 fin configuration for ultra performance, a 2-1 fin configuration for best power efficiency and transistor density, and a 2-2 fin configuration providing a balance between the two for Efficient Performance. With TSMC FINFLEX architecture, customers can create SoC designs precisely tuned for their needs with functional blocks implementing the best optimized fin configuration for the desired performance, power and area target, and integrated on the same chip. For more information on FINFLEX, please visit N3.TSMC.COM.

N2 Technology – TSMC’s N2 technology delivers either a 10-15% speed improvement at the same power, or 25-30% power reduction at the same speed compared to  N3. N2 will feature nanosheet transistor architecture to deliver a full-node improvement in performance and power efficiency to enable next-generation product innovations from TSMC customers. The N2 technology platform includes a high-performance variant in addition to the mobile compute baseline version, as well as comprehensive chiplet integration solutions. N2 is scheduled to begin production in 2025.

Expanding Ultra -Low Power Platform – To follow the 2020 N12e process, TSMC is developing N6e to provide the computing power and energy efficiency required by edge AI and IoT devices. N6e will be based on TSMC’s 7nm process and is expected to have three times greater logic density than N12e. It will serve as a part of TSMC’s Ultra-Low Power platform, a comprehensive portfolio of logic, RF, analog, embedded nonvolatile memory, and power management IC solutions aimed at applications in edge AI and the Internet of Things.

TSMC 3DFabric 3D Silicon Stacking Solutions – TSMC customer applications of the TSMC-SoIC chip stacking solution include:

1. The world’s first SoIC-based CPU employing Chip-on-Wafer (CoW) technology to stack SRAM as a Level 3 cache
2. A groundbreaking intelligence processing unit stacked on top of a deep trench capacitor die using Wafer-on-Wafer (WoW) technology.

With N7 chips already in production for both CoW and WoW, support for N5 technology is scheduled for 2023. To meet customer demand for SoIC and other TSMC 3DFabric system integration services, the world’s first fully automated 3DFabric factory is set to begin production in the second half of 2022.